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SubjectRe: [PATCH] arm64: cpufeature: Export Armv8.6 Matrix feature to userspace
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Hi Will,

On 29/10/2019 11:15, Will Deacon wrote:
> On Fri, Oct 25, 2019 at 06:10:56PM +0100, Julien Grall wrote:
>> This patch provides support for reporting the presence of Armv8.6
>> Matrix and its optional features to userspace.
>
> Are you sure this is 8.6 and not earlier?

This was introduced by Armv8.6 see [1] but allowed to be used by Armv8.2 and
onwards.

>
>> This based on [1] + commit ec52c7134b1f "arm64: cpufeature: Treat
>> ID_AA64ZFR0_EL1 as RAZ when SVE is not enabled" (taken from v5.4-rc4).
>>
>> [1] arm64/for-next/elf-hwcap-docs
>> ---
>> Documentation/arm64/cpu-feature-registers.rst | 8 ++++++++
>> Documentation/arm64/elf_hwcaps.rst | 15 +++++++++++++++
>> arch/arm64/include/asm/hwcap.h | 4 ++++
>> arch/arm64/include/asm/sysreg.h | 7 +++++++
>> arch/arm64/include/uapi/asm/hwcap.h | 4 ++++
>> arch/arm64/kernel/cpufeature.c | 11 +++++++++++
>> arch/arm64/kernel/cpuinfo.c | 4 ++++
>> 7 files changed, 53 insertions(+)
>>
>> diff --git a/Documentation/arm64/cpu-feature-registers.rst b/Documentation/arm64/cpu-feature-registers.rst
>> index ffcf4e2c71ef..d1d6d56a7b08 100644
>> --- a/Documentation/arm64/cpu-feature-registers.rst
>> +++ b/Documentation/arm64/cpu-feature-registers.rst
>> @@ -193,6 +193,8 @@ infrastructure:
>> +------------------------------+---------+---------+
>> | Name | bits | visible |
>> +------------------------------+---------+---------+
>> + | I8MM | [52-55] | y |
>> + +------------------------------+---------+---------+
>
> Looking at:
>
> https://developer.arm.com/docs/ddi0601/latest/aarch64-system-registers/id_aa64isar1_el1
>
> Then I8MM is advertised as "Armv8.2", alongside other fields that we haven't
> listed here such as BF16 and SPECRES.
>
> So we probably want a patch bringing all of this up to speed, rather than
> randomly advertising some features and not others.
>
>> | SB | [36-39] | y |
>> +------------------------------+---------+---------+
>> | FRINTTS | [32-35] | y |
>> @@ -227,6 +229,12 @@ infrastructure:
>> +------------------------------+---------+---------+
>> | Name | bits | visible |
>> +------------------------------+---------+---------+
>> + | F64MM | [56-59] | y |
>> + +------------------------------+---------+---------+
>> + | F32MM | [52-55] | y |
>> + +------------------------------+---------+---------+
>> + | I8MM | [44-47] | y |
>> + +------------------------------+---------+---------+
>
> Urgh, we're inconsistent in our bitfields. Some are [lo-hi] whilst others
> are [hi-lo]. Please can you fix that in a preparatory patch? I prefer
> [hi-lo] and it matches the arch docs.

Sure.

Cheers,

[1]
https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-architecture-developments-armv8-6-a

>
> Will
>

--
Julien Grall

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