Messages in this thread Patch in this message | | | From | Anvesh Salveru <> | Subject | [PATCH v2 2/2] PCI: dwc: Add support to handle ZRX-DC Compliant PHYs | Date | Mon, 28 Oct 2019 17:46:28 +0530 |
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Many platforms use DesignWare controller but the PHY can be different in different platforms. If the PHY is compliant to the ZRX-DC specification it helps lower power consumption during power states.
If current data rate is 8.0 GT/s or higher and PHY is not compliant to ZRX-DC specification, then after every 100ms link should transition to recovery state during the low power states.
DesignWare controller provides GEN3_ZRXDC_NONCOMPL field in GEN3_RELATED_OFF to specify about ZRX-DC compliant PHY.
Platforms with ZRX-DC compliant PHY can set "snps,phy-zrxdc-compliant" property in controller DT node to specify this property to the controller.
CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> CC: Andrew Murray <andrew.murray@arm.com> Signed-off-by: Anvesh Salveru <anvesh.s@samsung.com> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> --- Change in v2: - trivial change in patch description
drivers/pci/controller/dwc/pcie-designware.c | 7 +++++++ drivers/pci/controller/dwc/pcie-designware.h | 3 +++ 2 files changed, 10 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 820488dfeaed..6560d9f765d7 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -556,4 +556,11 @@ void dw_pcie_setup(struct dw_pcie *pci) PCIE_PL_CHK_REG_CHK_REG_START; dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); } + + if (of_property_read_bool(np, "snps,phy-zrxdc-compliant")) { + val = dw_pcie_readl_dbi(pci, PCIE_PORT_GEN3_RELATED); + val &= ~PORT_LOGIC_GEN3_ZRXDC_NONCOMPL; + dw_pcie_writel_dbi(pci, PCIE_PORT_GEN3_RELATED, val); + } + } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 5a18e94e52c8..427a55ec43c6 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -60,6 +60,9 @@ #define PCIE_MSI_INTR0_MASK 0x82C #define PCIE_MSI_INTR0_STATUS 0x830 +#define PCIE_PORT_GEN3_RELATED 0x890 +#define PORT_LOGIC_GEN3_ZRXDC_NONCOMPL BIT(0) + #define PCIE_ATU_VIEWPORT 0x900 #define PCIE_ATU_REGION_INBOUND BIT(31) #define PCIE_ATU_REGION_OUTBOUND 0 -- 2.17.1
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