lkml.org 
[lkml]   [2019]   [Oct]   [27]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
From
Subject[PATCH v2 0/5] add the DDR clock controller on Meson8 and Meson8b
Date
Meson8 and Meson8b SoCs embed a DDR clock controller in their MMCBUS
registers. This series:
- adds support for this DDR clock controller (patches 0 and 1)
- wires up the DDR PLL as input for two audio clocks (patches 2 and 3)
- adds the DDR clock controller to meson8.dtsi and meson8b.dtsi

Special thanks go out to Alexandre Mergnat for switching the Amlogic
clock drivers over to parent_hws and parent_data. That made this series
a lot easier for me!

This series depends on v2 my other series from [0]:
"provide the XTAL clock via OF on Meson8/8b/8m2"

Changes since v1 at [1]:
- fixed the license of the .yaml binding and added Rob's Reviewed-by
- drop unused syscon.h include (spotted by Jerome - thanks)
- drop fast_io from regmap_config and add max_register as suggested
by Jerome
- dropped original patch #4 "clk: meson: meson8b: add the ddr_pll
input for the audio clocks" because I could not test that yet (that
patch was a forward-port from Amlogic's 3.10 BSP kernel)


[0] https://patchwork.kernel.org/cover/11214189/
[1] https://patchwork.kernel.org/cover/11155553/


Martin Blumenstingl (5):
dt-bindings: clock: add the Amlogic Meson8 DDR clock controller
binding
clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller
clk: meson: meson8b: use of_clk_hw_register to register the clocks
ARM: dts: meson8: add the DDR clock controller
ARM: dts: meson8b: add the DDR clock controller

.../clock/amlogic,meson8-ddr-clkc.yaml | 50 ++++++
arch/arm/boot/dts/meson8.dtsi | 13 +-
arch/arm/boot/dts/meson8b.dtsi | 13 +-
drivers/clk/meson/Makefile | 2 +-
drivers/clk/meson/meson8-ddr.c | 152 ++++++++++++++++++
drivers/clk/meson/meson8b.c | 2 +-
include/dt-bindings/clock/meson8-ddr-clkc.h | 4 +
7 files changed, 230 insertions(+), 6 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml
create mode 100644 drivers/clk/meson/meson8-ddr.c
create mode 100644 include/dt-bindings/clock/meson8-ddr-clkc.h

--
2.23.0

\
 
 \ /
  Last update: 2019-10-27 17:25    [W:1.821 / U:0.024 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site