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SubjectRe: [PATCH v2 1/2] dmaengine: avalon: Intel Avalon-MM DMA Interface for PCIe
On Tue, Oct 15, 2019 at 01:24:50PM +0200, Alexander Gordeev wrote:
> On Thu, Oct 10, 2019 at 02:30:34PM +0300, Dan Carpenter wrote:
> > On Thu, Oct 10, 2019 at 10:51:45AM +0200, Alexander Gordeev wrote:
> > > On Wed, Oct 09, 2019 at 09:53:23PM +0300, Dan Carpenter wrote:
> > > > > > > + u32 *rd_flags = hw->dma_desc_table_rd.cpu_addr->flags;
> > > > > > > + u32 *wr_flags = hw->dma_desc_table_wr.cpu_addr->flags;
> > > > > > > + struct avalon_dma_desc *desc;
> > > > > > > + struct virt_dma_desc *vdesc;
> > > > > > > + bool rd_done;
> > > > > > > + bool wr_done;
> > > > > > > +
> > > > > > > + spin_lock(lock);
>
> [*]
>
> > > > > > > +
> > > > > > > + rd_done = (hw->h2d_last_id < 0);
> > > > > > > + wr_done = (hw->d2h_last_id < 0);
> > > > > > > +
> > > > > > > + if (rd_done && wr_done) {
> > > > > > > + spin_unlock(lock);
> > > > > > > + return IRQ_NONE;
> > > > > > > + }
> > > > > > > +
> > > > > > > + do {
> > > > > > > + if (!rd_done && rd_flags[hw->h2d_last_id])
> > > > > > > + rd_done = true;
> > > > > > > +
> > > > > > > + if (!wr_done && wr_flags[hw->d2h_last_id])
> > > > > > > + wr_done = true;
> > > > > > > + } while (!rd_done || !wr_done);


Thinking about this some more, my initial instinct was still correct
actually. If we're holding the lock to prevent the CPU from writing
to it then how is hw->d2h_last_id updated in the other thread? Either
it must deadlock or it must be a race condition.

regards,
dan carpenter

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