Messages in this thread | | | Date | Mon, 14 Oct 2019 21:29:38 +0200 | From | Thomas Petazzoni <> | Subject | Re: [PATCH v2] PCI: aardvark: Wait for endpoint to be ready before training link |
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Hello Remi,
On Wed, 22 May 2019 23:33:50 +0200 Remi Pommarel <repk@triplefau.lt> wrote:
> When configuring pcie reset pin from gpio (e.g. initially set by > u-boot) to pcie function this pin goes low for a brief moment > asserting the PERST# signal. Thus connected device enters fundamental > reset process and link configuration can only begin after a minimal > 100ms delay (see [1]). > > Because the pin configuration comes from the "default" pinctrl it is > implicitly configured before the probe callback is called: > > driver_probe_device() > really_probe() > ... > pinctrl_bind_pins() /* Here pin goes from gpio to PCIE reset > function and PERST# is asserted */ > ... > drv->probe() > > [1] "PCI Express Base Specification", REV. 4.0 > PCI Express, February 19 2014, 6.6.1 Conventional Reset > > Signed-off-by: Remi Pommarel <repk@triplefau.lt>
It is always a bit annoying to add another 100ms in the boot path, but I don't see an easy alternative solution, so:
Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Thomas -- Thomas Petazzoni, CTO, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
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