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    SubjectRe: [PATCH] arm64: cpufeature: Don't expose ZFR0 to userspace when SVE is not enabled
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    Hi Julien,

    Some minor nits in the description.

    On 14/10/2019 11:21, Julien Grall wrote:
    > The kernel may not support SVE if CONFIG_ARM64_SVE is not set and
    > will hide the feature from the from userspace.
    >
    > Unfortunately, the fields of ID_AA64ZFR0_EL1 are still exposed and could
    > lead to undefined behavior in userspace.
    >
    > The kernel should not used the register when CONFIG_SVE is disabled.

    s/used/use ?

    > Therefore, we only need to hidden them from the userspace.

    s/hidden/hide ?

    With the above:

    Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>

    >
    > Signed-off-by: Julien Grall <julien.grall@arm.com>
    > Fixes: 06a916feca2b ('arm64: Expose SVE2 features for userspace')
    > ---
    > arch/arm64/kernel/cpufeature.c | 15 ++++++++++-----
    > 1 file changed, 10 insertions(+), 5 deletions(-)
    >
    > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
    > index cabebf1a7976..80f459ad0190 100644
    > --- a/arch/arm64/kernel/cpufeature.c
    > +++ b/arch/arm64/kernel/cpufeature.c
    > @@ -176,11 +176,16 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
    > };
    >
    > static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
    > - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
    > - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
    > - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
    > - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
    > - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
    > + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
    > + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
    > + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
    > + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
    > + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
    > + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
    > + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
    > + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
    > + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
    > + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
    > ARM64_FTR_END,
    > };
    >
    >

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