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Subject[PATCH 2/2] DTS: CI20: Add CPU nodes and L2 cache nodes.
Date
Current kernels complain when booting on CI20:
[ 0.329630] cacheinfo: Failed to find cpu0 device node
[ 0.335023] cacheinfo: Unable to detect cache hierarchy for CPU 0
Add the CPU node and the L2 cache node, then let each CPU point to it.

Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
arch/mips/boot/dts/ingenic/jz4780.dtsi | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)

diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi
index b03cdec..7c0a853 100644
--- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
@@ -7,6 +7,31 @@
#size-cells = <1>;
compatible = "ingenic,jz4780";

+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "ingenic,xburst";
+ reg = <0>;
+ next-level-cache = <&l2c>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "ingenic,xburst";
+ reg = <1>;
+ next-level-cache = <&l2c>;
+ clocks = <&cgu JZ4780_CLK_CORE1>;
+ };
+
+ l2c: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
--
2.7.4

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