lkml.org 
[lkml]   [2019]   [Jan]   [29]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH 4.20 036/117] clk: socfpga: stratix10: fix rate calculation for pll clocks
    Date
    4.20-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Dinh Nguyen <dinguyen@kernel.org>

    commit c0a636e4cc2eb39244d23c0417c117be4c96a7fe upstream.

    The main PLL calculation has a mistake. We should be using the
    multiplying the VCO frequency, not the parent clock frequency.

    Fixes: 07afb8db7340 ("clk: socfpga: stratix10: add clock driver for
    Stratix10 platform")
    Cc: linux-stable@vger.kernel.org
    Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
    Signed-off-by: Stephen Boyd <sboyd@kernel.org>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    drivers/clk/socfpga/clk-pll-s10.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    --- a/drivers/clk/socfpga/clk-pll-s10.c
    +++ b/drivers/clk/socfpga/clk-pll-s10.c
    @@ -43,7 +43,7 @@ static unsigned long clk_pll_recalc_rate
    /* Read mdiv and fdiv from the fdbck register */
    reg = readl(socfpgaclk->hw.reg + 0x4);
    mdiv = (reg & SOCFPGA_PLL_MDIV_MASK) >> SOCFPGA_PLL_MDIV_SHIFT;
    - vco_freq = (unsigned long long)parent_rate * (mdiv + 6);
    + vco_freq = (unsigned long long)vco_freq * (mdiv + 6);

    return (unsigned long)vco_freq;
    }

    \
     
     \ /
      Last update: 2019-01-29 12:38    [W:5.076 / U:0.124 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site