Messages in this thread Patch in this message | | | From | Jonas Bonn <> | Subject | [PATCH v3 2/2] spi-atmel: support inter-word delay | Date | Sat, 26 Jan 2019 17:32:20 +0100 |
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If the SPI slave requires an inter-word delay, configure the DLYBCT register accordingly.
Tested on a SAMA5D2 board (derived from SAMA5D2-Xplained reference board).
Signed-off-by: Jonas Bonn <jonas@norrbonn.se> CC: Nicolas Ferre <nicolas.ferre@microchip.com> CC: Mark Brown <broonie@kernel.org> CC: Alexandre Belloni <alexandre.belloni@bootlin.com> CC: Ludovic Desroches <ludovic.desroches@microchip.com> CC: linux-spi@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org --- drivers/spi/spi-atmel.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c index 74fddcd3282b..24445bfbd74e 100644 --- a/drivers/spi/spi-atmel.c +++ b/drivers/spi/spi-atmel.c @@ -1209,13 +1209,21 @@ static int atmel_spi_setup(struct spi_device *spi) csr |= SPI_BIT(CSAAT); /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs. - * - * DLYBCT would add delays between words, slowing down transfers. - * It could potentially be useful to cope with DMA bottlenecks, but - * in those cases it's probably best to just use a lower bitrate. */ csr |= SPI_BF(DLYBS, 0); - csr |= SPI_BF(DLYBCT, 0); + + /* DLYBCT adds delays between words. This is useful for slow devices + * that need a bit of time to setup the next transfer. + */ + if (spi->word_delay) { + csr |= SPI_BF(DLYBCT, + clamp_t(u8, + (as->spi_clk/1000000*spi->word_delay)>>5, + 1, 255)); + } else { + csr |= SPI_BF(DLYBCT, 0); + } + /* chipselect must have been muxed as GPIO (e.g. in board setup) */ npcs_pin = (unsigned long)spi->controller_data; -- 2.19.1
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