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Subject[PATCH 0/3] iommu/arm-smmu: Add support to use Last level cache
Qualcomm SoCs have an additional level of cache called as
System cache, aka. Last level cache (LLC). This cache sits right
before the DDR, and is tightly coupled with the memory controller.
The clients using this cache request their slices from this
system cache, make it active, and can then start using it.
For these clients with smmu, to start using the system cache for
buffers and, related page tables [1], memory attributes need to be
set accordingly. This series add the required support.

This change is a realisation of following changes from downstream msm-4.9:
iommu: io-pgtable-arm: Support DOMAIN_ATTRIBUTE_USE_UPSTREAM_HINT[2]
iommu: io-pgtable-arm: Implement IOMMU_USE_UPSTREAM_HINT[3]

Changes since v2:
- Split the patches into io-pgtable-arm driver and arm-smmu driver.
- Converted smmu domain attributes to a bitmap, so multiple attributes
can be managed easily.
- With addition of non-coherent page table mapping support [4], this
patch series now aligns with the understanding of upgrading the
non-coherent devices to use some level of outer cache.
- Updated the macros and comments to reflect the use of QCOM_SYS_CACHE.
- QCOM_SYS_CACHE can still be used at stage 2, so that doens't depend on
stage-1 mapping.
- Added change to disable the attribute from arm_smmu_domain_set_attr()
when needed.
- Removed the page protection controls for QCOM_SYS_CACHE at the DMA API

Goes on top of the non-coherent page tables support patch series [4]


Vivek Gautam (3):
iommu/arm-smmu: Move to bitmap for arm_smmu_domain atrributes
iommu/io-pgtable-arm: Add support to use system cache
iommu/arm-smmu: Add support to use system cache

drivers/iommu/arm-smmu.c | 28 ++++++++++++++++++++++++----
drivers/iommu/io-pgtable-arm.c | 15 +++++++++++++--
drivers/iommu/io-pgtable.h | 4 ++++
include/linux/iommu.h | 2 ++
4 files changed, 43 insertions(+), 6 deletions(-)

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of Code Aurora Forum, hosted by The Linux Foundation

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