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Subject[PATCH v1 6/8] phy: qcom-qmp: Utilize UFS reset controller
Date
Request the newly minted reset controller from the Qualcomm UFS
controller, and use it to toggle the PHY reset line from within
the PHY. This will allow us to merge the two phases of UFS PHY
initialization.

Signed-off-by: Evan Green <evgreen@chromium.org>

---
Note: this change is dependent on the previous changes, including
the DT changes, in order to expose the reset controller from UFS.

drivers/phy/qualcomm/phy-qcom-qmp.c | 45 +++++++++++++++++++++++++++++
1 file changed, 45 insertions(+)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index b4006818e1b65..eb1cac8f0fd4e 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -739,6 +739,9 @@ struct qmp_phy_cfg {

/* true, if PCS block has no separate SW_RESET register */
bool no_pcs_sw_reset;
+
+ /* true if the PHY has a UFS reset control to toggle */
+ bool has_ufsphy_reset;
};

/**
@@ -787,6 +790,7 @@ struct qmp_phy {
* @init_count: phy common block initialization count
* @phy_initialized: indicate if PHY has been initialized
* @mode: current PHY mode
+ * @ufs_reset: optional UFS PHY reset handle
*/
struct qcom_qmp {
struct device *dev;
@@ -804,6 +808,8 @@ struct qcom_qmp {
int init_count;
bool phy_initialized;
enum phy_mode mode;
+
+ struct reset_control *ufs_reset;
};

static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
@@ -1034,6 +1040,8 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {

.is_dual_lane_phy = true,
.no_pcs_sw_reset = true,
+
+ .has_ufsphy_reset = true,
};

static void qcom_qmp_phy_configure(void __iomem *base,
@@ -1177,6 +1185,9 @@ static int qcom_qmp_phy_com_exit(struct qcom_qmp *qmp)
return 0;
}

+ if (qmp->ufs_reset)
+ reset_control_assert(qmp->ufs_reset);
+
if (cfg->has_phy_com_ctrl) {
qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
SERDES_START | PCS_START);
@@ -1214,6 +1225,32 @@ static int qcom_qmp_phy_init(struct phy *phy)

dev_vdbg(qmp->dev, "Initializing QMP phy\n");

+ if (cfg->has_ufsphy_reset) {
+ /*
+ * Get UFS reset, which is delayed until now to avoid a
+ * circular dependency where UFS needs its PHY, but the PHY
+ * needs this UFS reset.
+ */
+ if (!qmp->ufs_reset) {
+ qmp->ufs_reset = of_reset_control_get(qmp->dev->of_node,
+ "ufsphy");
+
+ if (IS_ERR(qmp->ufs_reset)) {
+ dev_err(qmp->dev,
+ "failed to get UFS reset: %d\n",
+ PTR_ERR(qmp->ufs_reset));
+
+ return PTR_ERR(qmp->ufs_reset);
+ }
+ }
+
+ ret = reset_control_assert(qmp->ufs_reset);
+ if (ret) {
+ dev_err(qmp->dev, "ufsphy reset deassert failed\n");
+ goto err_lane_rst;
+ }
+ }
+
ret = qcom_qmp_phy_com_init(qphy);
if (ret)
return ret;
@@ -1247,6 +1284,14 @@ static int qcom_qmp_phy_init(struct phy *phy)

qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);

+ if (qmp->ufs_reset) {
+ ret = reset_control_deassert(qmp->ufs_reset);
+ if (ret) {
+ dev_err(qmp->dev, "ufsphy reset deassert failed\n");
+ goto err_lane_rst;
+ }
+ }
+
/*
* UFS PHY requires the deassert of software reset before serdes start.
* For UFS PHYs that do not have software reset control bits, defer
--
2.18.1
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