Messages in this thread | | | Date | Tue, 4 Sep 2018 18:11:14 +0200 | From | Wolfram Sang <> | Subject | Re: [PATCH] i2c: xiic: Make the start and the byte count write atomic |
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On Mon, Sep 03, 2018 at 03:11:11PM +0530, shubhrajyoti.datta@gmail.com wrote: > From: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> > > Disable interrupts while configuring the transfer and enable them back. > > We have below as the programming sequence > 1. start and slave address > 2. byte count and stop > > In some customer platform there was a lot of interrupts between 1 and 2 > and after slave address (around 7 clock cyles) if 2 is not executed > then the transaction is nacked. > > To fix this case make the 2 writes atomic. > > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> > Signed-off-by: Michal Simek <michal.simek@xilinx.com>
I assume simply changing the order of the register writes won't fix it?
I also assume this is stable material?
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