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SubjectRe: [PATCH v2 1/4] pinctrl: qcom: Introduce readl/writel accessors
On Fri, Sep 28, 2018 at 9:10 AM Linus Walleij <linus.walleij@linaro.org> wrote:

> This clashes with Stephen Boyds fix:
> "pinctrl: msm: Really mask level interrupts to prevent latching"
>
> I've resolved it like this:

Also this:
static void msm_gpio_irq_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
const struct msm_pingroup *g;
unsigned long flags;
u32 val;

g = &pctrl->soc->groups[d->hwirq];

raw_spin_lock_irqsave(&pctrl->lock, flags);

val = msm_readl_intr_cfg(pctrl, g);
val |= BIT(g->intr_raw_status_bit);
val |= BIT(g->intr_enable_bit);
msm_writel_intr_cfg(val, pctrl, g);

set_bit(d->hwirq, pctrl->enabled_irqs);

raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}

Yours,
Linus Walleij

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