Messages in this thread | | | Date | Thu, 27 Sep 2018 16:41:12 +0200 (CEST) | From | Thomas Gleixner <> | Subject | Re: [patch 09/11] x86/vdso: Simplify the invalid vclock case |
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On Tue, 18 Sep 2018, Thomas Gleixner wrote: > On Tue, 18 Sep 2018, Thomas Gleixner wrote: > > So if the TSC on CPU1 is slightly behind the TSC on CPU0 then now1 can be > > smaller than cycle_last. The TSC sync stuff does not catch the small delta > > for unknown raisins. I'll go and find that machine and test that again. > > Of course it does not trigger anymore. We accumulated code between the > point in timekeeping_advance() where the TSC is read and the update of the > VDSO data. > > I'll might have to get an 2.6ish kernel booted on that machine and try with > that again. /me shudders
Actually it does happen, because the TSC is very slowly drifting apart due to SMI wreckage trying to hide itself. It just takes a very long time.
Thanks,
tglx
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