Messages in this thread Patch in this message | | | Date | Wed, 19 Sep 2018 10:50:20 +0200 | From | Peter Zijlstra <> | Subject | [PATCH 4/8] x86/mm/cpa: Use flush_tlb_kernel_range() |
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Both cpa_flush_range() and cpa_flush_array() have a well specified range, use that to do a range based TLB invalidate.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> --- arch/x86/mm/pageattr.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-)
--- a/arch/x86/mm/pageattr.c +++ b/arch/x86/mm/pageattr.c @@ -293,7 +293,7 @@ static void cpa_flush_range(unsigned lon BUG_ON(irqs_disabled() && !early_boot_irqs_disabled); WARN_ON(PAGE_ALIGN(start) != start); - flush_tlb_all(); + flush_tlb_kernel_range(start, start + PAGE_SIZE * numpages); if (!cache) return; @@ -315,14 +315,15 @@ static void cpa_flush_range(unsigned lon } } -static void cpa_flush_array(unsigned long *start, int numpages, int cache, +static void cpa_flush_array(unsigned long baddr, unsigned long *start, + int numpages, int cache, int in_flags, struct page **pages) { unsigned int i, level; BUG_ON(irqs_disabled() && !early_boot_irqs_disabled); - flush_tlb_all(); + flush_tlb_kernel_range(baddr, baddr + PAGE_SIZE * numpages); if (!cache) return; @@ -1754,7 +1755,7 @@ static int change_page_attr_set_clr(unsi */ if (!ret && boot_cpu_has(X86_FEATURE_CLFLUSH)) { if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) { - cpa_flush_array(addr, numpages, cache, + cpa_flush_array(baddr, addr, numpages, cache, cpa.flags, pages); } else cpa_flush_range(baddr, numpages, cache);
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