Messages in this thread | | | Date | Fri, 31 Aug 2018 12:49:45 +0200 | From | Peter Zijlstra <> | Subject | Re: [PATCH 00/12] Avoid synchronous TLB invalidation for intermediate page-table entries on arm64 |
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On Fri, Aug 31, 2018 at 08:32:34PM +1000, Nicholas Piggin wrote: > Oh gee, I suppose. powerpc hash is kind of interesting because it's > crazy, Aneesh knows that code a lot better than I do. radix modulo > some minor details of exact instructions is fairly like x86
The whole TLB broadcast vs explicit IPIs is a fairly big difference in my book.
Anyway, have you guys tried the explicit IPI approach? Depending on how IPIs are routed vs broadcasts it might save a little bus traffic. No point in getting all CPUs to process the TLBI when there's only a hand full that really need it.
OTOH, I suppose the broadcast thing has been optimized to death on the hardware side, so who knows..
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