Messages in this thread | | | From | Chen-Yu Tsai <> | Date | Sat, 11 Aug 2018 00:48:19 +0800 | Subject | Re: [PATCH] clk: sunxi-ng: h6: fix PWM gate/reset offset |
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On Fri, Aug 10, 2018 at 11:16 PM, Icenowy Zheng <icenowy@aosc.io> wrote: > From: Rongyi Chen <chenyi@tt-cool.com> > > Currently the register offset of the PWM bus gate in Allwinner H6 clock > driver is wrong. > > Fix this issue. > > Fixes: 542353ea ("clk: sunxi-ng: add support for the Allwinner H6 CCU") > Signed-off-by: Rongyi Chen <chenyi@tt-cool.com> > [Icenowy: refactor commit message] > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Queued up for 4.20. Thanks
ChenYu
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