Messages in this thread | | | Date | Sat, 07 Jul 2018 20:55:21 +0900 (KST) | Subject | Re: [PATCH v2 2/2] net: macb: Allocate valid memory for TX and RX BD prefetch | From | David Miller <> |
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From: Harini Katakam <harini.katakam@xilinx.com> Date: Fri, 6 Jul 2018 12:18:58 +0530
> GEM version in ZynqMP and most versions greater than r1p07 supports > TX and RX BD prefetch. The number of BDs that can be prefetched is a > HW configurable parameter. For ZynqMP, this parameter is 4. > > When GEM DMA is accessing the last BD in the ring, even before the > BD is processed and the WRAP bit is noticed, it will have prefetched > BDs outside the BD ring. These will not be processed but it is > necessary to have accessible memory after the last BD. Especially > in cases where SMMU is used, memory locations immediately after the > last BD may not have translation tables triggering HRESP errors. Hence > always allocate extra BDs to accommodate for prefetch. > The value of tx/rx bd prefetch for any given SoC version is: > 2 ^ (corresponding field in design config 10 register). > (value of this field >= 1) > > Added a capability flag so that older IP versions that do not have > DCFG10 or this prefetch capability are not affected. > > Signed-off-by: Harini Katakam <harini.katakam@xilinx.com> > Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Applied.
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