Messages in this thread | | | From | Stephen Boyd <> | Subject | Re: [PATCH v6 3/4] clk: tegra: Add sdmmc mux divider clock | Date | Wed, 25 Jul 2018 14:28:18 -0700 |
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Quoting Aapo Vienamo (2018-07-12 04:53:01) > From: Peter De-Schrijver <pdeschrijver@nvidia.com> > > Add a clock type to model the sdmmc switch divider clocks which have paths > to source clocks bypassing the divider (Low Jitter paths). These > are handled by selecting the lj path when the divider is 1 (ie the > rate is the parent rate), otherwise the normal path with divider > will be selected. Otherwise this clock behaves as a normal peripheral > clock. > > Signed-off-by: Peter De-Schrijver <pdeschrijver@nvidia.com> > Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> > Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> > ---
Applied to clk-next
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