Messages in this thread | | | Date | Mon, 2 Jul 2018 15:13:00 +0200 | From | Thierry Reding <> | Subject | Re: [PATCH v3 5/8] mailbox: tegra-hsp: Add support for shared mailboxes |
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On Mon, Jul 02, 2018 at 02:40:30PM +0300, Mikko Perttunen wrote: > The Tegra HSP block supports 'shared mailboxes' that are simple 32-bit > registers consisting of a FULL bit in MSB position and 31 bits of data. > The hardware can be configured to trigger interrupts when a mailbox > is empty or full. Add support for these shared mailboxes to the HSP > driver. > > The initial use for the mailboxes is the Tegra Combined UART. For this > purpose, we use interrupts to receive data, and spinning to wait for > the transmit mailbox to be emptied to minimize unnecessary overhead. > > Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> > Reviewed-by: Jon Hunter <jonathanh@nvidia.com> > --- > > Notes: > v3: > - Added define HSP_INT0_IE_FULL_SHIFT > - Added Jon's Reviewed-by > > v2: > - Added defines for some register fields > - Simplified bit looping logic in interrupt handler > - Changed write done polling to use readl_poll_timeout > - Removed unnecessary zero assignments > - Fixed two error cases in probe to do proper cleanup > > drivers/mailbox/tegra-hsp.c | 211 +++++++++++++++++++++++++++++++++++++++----- > 1 file changed, 191 insertions(+), 20 deletions(-)
Looks good to me:
Acked-by: Thierry Reding <treding@nvidia.com> [unhandled content-type:application/pgp-signature] | |