Messages in this thread Patch in this message | | | Date | Mon, 02 Jul 2018 04:47:57 -0600 | From | "Jan Beulich" <> | Subject | [PATCH] x86/entry/64: add two more instruction suffixes |
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Sadly, other than claimed in a368d7fd2a ("x86/entry/64: Add instruction suffix"), there are two more instances which want to be adjusted. As said there, omitting suffixes from instructions in AT&T mode is bad practice when operand size cannot be determined by the assembler from register operands, and is likely going to be warned about by upstream gas in the future (mine does already). Add the other missing suffixes here as well.
Signed-off-by: Jan Beulich <jbeulich@suse.com> --- arch/x86/entry/entry_64.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
--- 4.18-rc3/arch/x86/entry/entry_64.S +++ 4.18-rc3-x86_64-entry-insn-suffix/arch/x86/entry/entry_64.S @@ -92,7 +92,7 @@ END(native_usergs_sysret64) .endm .macro TRACE_IRQS_IRETQ_DEBUG - bt $9, EFLAGS(%rsp) /* interrupts off? */ + btl $9, EFLAGS(%rsp) /* interrupts off? */ jnc 1f TRACE_IRQS_ON_DEBUG 1: @@ -701,7 +701,7 @@ retint_kernel: #ifdef CONFIG_PREEMPT /* Interrupts are off */ /* Check if we need preemption */ - bt $9, EFLAGS(%rsp) /* were interrupts off? */ + btl $9, EFLAGS(%rsp) /* were interrupts off? */ jnc 1f 0: cmpl $0, PER_CPU_VAR(__preempt_count) jnz 1f
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