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    Subject[PATCH 3.16 172/410] staging: iio: adc: remove the use of CamelCase
    3.16.57-rc1 review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Ioana Ciornei <ciorneiioana@gmail.com>

    commit 5f7e280f5ae61450a7aecd9feefe3f032b6a5abf upstream.

    Remove the use of CamelCase to follow the kernel naming conventions

    Signed-off-by: Ioana Ciornei <ciorneiioana@gmail.com>
    Reviewed-by: Daniel Baluta <daniel.baluta@intel.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    [bwh: Backported to 3.16: adjust context]
    Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
    ---
    drivers/staging/iio/adc/ad7192.c | 10 +++++-----
    drivers/staging/iio/adc/ad7192.h | 2 +-
    drivers/staging/iio/adc/ad7280a.c | 4 ++--
    3 files changed, 8 insertions(+), 8 deletions(-)

    --- a/drivers/staging/iio/adc/ad7192.c
    +++ b/drivers/staging/iio/adc/ad7192.c
    @@ -125,7 +125,7 @@
    #define AD7192_GPOCON_P1DAT (1 << 1) /* P1 state */
    #define AD7192_GPOCON_P0DAT (1 << 0) /* P0 state */

    -#define AD7192_INT_FREQ_MHz 4915200
    +#define AD7192_INT_FREQ_MHZ 4915200

    /* NOTE:
    * The AD7190/2/5 features a dual use data out ready DOUT/RDY output.
    @@ -226,14 +226,14 @@ static int ad7192_setup(struct ad7192_st
    switch (pdata->clock_source_sel) {
    case AD7192_CLK_EXT_MCLK1_2:
    case AD7192_CLK_EXT_MCLK2:
    - st->mclk = AD7192_INT_FREQ_MHz;
    + st->mclk = AD7192_INT_FREQ_MHZ;
    break;
    case AD7192_CLK_INT:
    case AD7192_CLK_INT_CO:
    - if (pdata->ext_clk_Hz)
    - st->mclk = pdata->ext_clk_Hz;
    + if (pdata->ext_clk_hz)
    + st->mclk = pdata->ext_clk_hz;
    else
    - st->mclk = AD7192_INT_FREQ_MHz;
    + st->mclk = AD7192_INT_FREQ_MHZ;
    break;
    default:
    ret = -EINVAL;
    --- a/drivers/staging/iio/adc/ad7192.h
    +++ b/drivers/staging/iio/adc/ad7192.h
    @@ -34,7 +34,7 @@
    struct ad7192_platform_data {
    u16 vref_mv;
    u8 clock_source_sel;
    - u32 ext_clk_Hz;
    + u32 ext_clk_hz;
    bool refin2_en;
    bool rej60_en;
    bool sinc3_en;
    --- a/drivers/staging/iio/adc/ad7280a.c
    +++ b/drivers/staging/iio/adc/ad7280a.c
    @@ -89,7 +89,7 @@

    #define AD7280A_ALL_CELLS (0xAD << 16)

    -#define AD7280A_MAX_SPI_CLK_Hz 700000 /* < 1MHz */
    +#define AD7280A_MAX_SPI_CLK_HZ 700000 /* < 1MHz */
    #define AD7280A_MAX_CHAIN 8
    #define AD7280A_CELLS_PER_DEV 6
    #define AD7280A_BITS 12
    @@ -850,7 +850,7 @@ static int ad7280_probe(struct spi_devic

    ad7280_crc8_build_table(st->crc_tab);

    - st->spi->max_speed_hz = AD7280A_MAX_SPI_CLK_Hz;
    + st->spi->max_speed_hz = AD7280A_MAX_SPI_CLK_HZ;
    st->spi->mode = SPI_MODE_1;
    spi_setup(st->spi);

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