[lkml]   [2018]   [Jun]   [6]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
SubjectRe: [PATCH v2 0/5] Tegra20 External Memory Controller driver
On Mon, Jun 04, 2018 at 01:36:49AM +0300, Dmitry Osipenko wrote:
> Hello,
> Couple years ago the Tegra20 EMC driver was removed from the kernel
> due to incompatible changes in the Tegra's clock driver. This patchset
> introduces a modernized EMC driver. Currently the sole purpose of the
> driver is to initialize DRAM frequency to maximum rate during of the
> kernels boot-up. Later we may consider implementing dynamic memory
> frequency scaling, utilizing functionality provided by this driver.
> Changelog:
> v2:
> - Minor code cleanups like consistent use of writel_relaxed instead
> of non-relaxed version, reworded error messages, etc.
> - Factored out use_pllm_ud bit checking into a standalone patch for
> consistency.
> Dmitry Osipenko (5):
> dt: bindings: tegra20-emc: Document interrupt property
> ARM: dts: tegra20: Add interrupt to External Memory Controller
> clk: tegra20: Turn EMC clock gate into divider
> clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC
> memory: tegra: Introduce Tegra20 EMC driver

I took a brief look and didn't spot any dependencies between the clk and
memory patches. Is it correct that these can be applied separately?

[unhandled content-type:application/pgp-signature]
 \ /
  Last update: 2018-06-06 12:47    [W:0.076 / U:0.700 seconds]
©2003-2018 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site