Messages in this thread | | | Subject | Re: [PATCH 3/6] coresight: Introduce support for Coresight Address Translation Unit | From | Suzuki K Poulose <> | Date | Thu, 21 Jun 2018 10:37:25 +0100 |
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Hi Mathieu,
On 20/06/1822:41, Mathieu Poirier wrote: > Hi Suzuki, > > On Mon, Jun 18, 2018 at 11:56:16AM +0100, Suzuki K Poulose wrote: >> Add the initial support for Coresight Address Translation Unit, which >> augments the TMC in Coresight SoC-600 by providing an improved Scatter >> Gather mechanism. CATU is always connected to a single TMC-ETR and >> converts the AXI address with a translated address (from a given SG >> table with specific format). The CATU should be programmed in pass >> through mode and enabled if the ETR doesn't translation by CATU. > > To me this sentence look broken. >
Yes, it is broken. It should have been :
"The CATU should be programmed in pass through mode and enabled even if the ETR doesn't use the translation by CATU."
>> +static int catu_disable_hw(struct catu_drvdata *drvdata) >> +{ >> + int rc = 0; >> + >> + if (catu_wait_for_ready(drvdata)) { >> + dev_info(drvdata->dev, "Timeout while waiting for READY\n"); >> + rc = -EAGAIN; >> + } >> + >> + catu_write_control(drvdata, 0); > > Is waiting for the ready bit before switching the component off comes from > experimentation with the HW (i.e FPGA)? From what the reference manual > indicate, CONTROL.ENABLE should be set to 0 first, and then wait for > STATUS.READY.
You're right. It should be in the reverse order. I will fix it in the next version.
Thanks Suzuki
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