Messages in this thread | | | Date | Sat, 5 May 2018 00:49:36 +0300 | From | "Kirill A. Shutemov" <> | Subject | Re: Proof-of-concept: better(?) page-table manipulation API |
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On Fri, May 04, 2018 at 09:12:44PM +0000, Matthew Wilcox wrote: > On Tue, Apr 24, 2018 at 06:43:56PM +0300, Kirill A. Shutemov wrote: > > +struct pt_ptr { > > + unsigned long *ptr; > > + int lvl; > > +}; > > On x86, you've got three kinds of paging scheme, referred to in the manual > as 32-bit, PAE and 4-level.
You forgot 5-level :)
(although it's not in the manual yet, so fair enough)
> On 32-bit, you've got 3 levels (Directory, Table and Entry), and you can > encode those three levels in the bottom two bits of the pointer. With > PAE and 4L, pointers are 64-bit aligned, so you can encode up to eight > levels in the bottom three bits of the pointer.
I didn't thought about this. Thank you.
> > +struct pt_val { > > + unsigned long val; > > + int lvl; > > +}; > > I don't think it's possible to shrink this down to a single ulong. > _Maybe_ it is if you can squirm a single bit free from the !pte_present > case.
I don't think it worth it. It gets tricky quickly.
> ... this is only for x86 4L and maybe 32 paging, right? It'd need to > use unsigned long val[2] for PAE.
I didn't look at 32-bit at all. But 4L and 5L [kinda] work.
> I'm going to think about this some more. There's a lot of potential here.
Thanks for the input.
-- Kirill A. Shutemov
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