[lkml]   [2018]   [May]   [29]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
SubjectRe: [PATCH] soc: imx: gpcv2: correct PGC offset
On Tue, 2018-05-29 at 16:02 +0800, Anson Huang wrote:
> Correct MIPI/PCIe/USB_HSIC's PGC offset based on
> design RTL, the value on Reference Manual are incorrect.
> The correct offset should be as below:
> -#define PGC_MIPI 4
> -#define PGC_PCIE 5
> -#define PGC_USB_HSIC 8
> +#define PGC_MIPI 16
> +#define PGC_PCIE 17
> +#define PGC_USB_HSIC 20
> #define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40)
> #define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc)

This gpcv2 driver is currently only used for PCI, it probably only
works because domains happen to be turned on by default?

On imx7d upstream platform suspend is not yet supported but even doing
device-level suspend causes a hang on resume somewhere in PCI on first
read. This patch fixes that immediate hang.

After suspend/resume lspci is broken (device doesn't properly resume),
that probably requires more imx pci patches and unrelated to pgc.


 \ /
  Last update: 2018-05-29 16:03    [W:0.067 / U:5.760 seconds]
©2003-2018 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site