Messages in this thread | | | Date | Mon, 28 May 2018 10:55:10 +0300 | From | Peter De Schrijver <> | Subject | Re: [PATCH v2 4/6] clk: tegra20: init NDFLASH clock to sensible rate |
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On Sun, May 27, 2018 at 11:54:40PM +0200, Stefan Agner wrote: > From: Lucas Stach <dev@lynxeye.de> > > Set up the NAND Flash controller clock to run at 150MHz > instead of the rate set by the bootloader. This is a > conservative rate which also yields good performance. > > Signed-off-by: Lucas Stach <dev@lynxeye.de> > Signed-off-by: Stefan Agner <stefan@agner.ch> > --- > drivers/clk/tegra/clk-tegra20.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c > index 0ee56dd04cec..dff8c425cd28 100644 > --- a/drivers/clk/tegra/clk-tegra20.c > +++ b/drivers/clk/tegra/clk-tegra20.c > @@ -1049,6 +1049,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { > { TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 }, > { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 }, > { TEGRA20_CLK_VDE, TEGRA20_CLK_CLK_MAX, 300000000, 0 }, > + { TEGRA20_CLK_NDFLASH, TEGRA20_CLK_PLL_P, 150000000, 0 }, > /* must be the last entry */ > { TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 }, > }; > -- > 2.17.0 >
Maybe better to specify this in the Tegra20 dtsi? See "Assigned clock parents and rates" in Documentation/devicetree/bindings/clock/clock-bindings.txt
Peter.
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