Messages in this thread Patch in this message | | | Subject | Re: [PATCH] mtd: nand: raw: atmel: add module param to avoid using dma | From | Peter Rosin <> | Date | Mon, 28 May 2018 00:11:07 +0200 |
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On 2018-05-27 11:18, Peter Rosin wrote: > On 2018-05-25 16:51, Tudor Ambarus wrote: >> We think the best way is to keep LCD on DDR Ports 2 and 3 (8th and 9th >> slaves), to have maximum bandwidth and to use DMA on DDR port 1 for NAND >> (7th slave). > > Exactly how do I accomplish that? > > I can see how I can move the LCD between slave DDR port 2 and 3 by > selecting LCDC DMA master 8 or 9 (but according to the above it should > not matter). The big question is how I control what slave the NAND flash > is going to use? I find nothing in the datasheet, and the code is also > non-transparent enough for me to figure it out by myself without > throwing out this question first...
I added this:
diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c index e686fe73159e..3b33c63d2ed4 100644 --- a/drivers/mtd/nand/raw/atmel/nand-controller.c +++ b/drivers/mtd/nand/raw/atmel/nand-controller.c @@ -1991,6 +1991,9 @@ static int atmel_nand_controller_init(struct atmel_nand_controller *nc, nc->dmac = dma_request_channel(mask, NULL, NULL); if (!nc->dmac) dev_err(nc->dev, "Failed to request DMA channel\n"); + + dev_info(nc->dev, "using %s for DMA transfers\n", + dma_chan_name(nc->dmac)); } /* We do not retrieve the SMC syscon when parsing old DTs. */
and the output is
atmel-nand-controller 10000000.ebi:nand-controller: using dma0chan5 for DMA transfers So, DMA controller 0 is in use. I still don't know if IF0, IF1 or IF2 is used or how to find out. I guess IF2 is not in use since that does not allow any DDR2 port as slave...
From the datasheet, DMAC0/IF0 uses DDR2 Port 2, and DMAC0/IF1 uses DDR2 Port 1. But, by the looks of the register content in my other mail, it seems as if DMA0/IF1 can also use DDR2 Port 3.
So, I think I want either
A) the NAND controller to use DMAC0/IF0 (i.e. DDR2 port 1, and possibly 3) and the LCDC to use master 9 (i.e. DDR2 Port 2)
or
B) the NAND controller to use DMAC1/IF1 (i.e. DDR2 port 2) and the LCDC to use master 8 (i.e. DDR2 Port 3)
But, again, how do I limit DMAC0 to either of IF0 or IF1 for NAND accesses?
Note that I have previously tried to move LCDC DMA from master 8 (the default) to master 9, and it got better, but not good enough. I.e. the visual glitches remained, but were a little bit harder to trigger. That makes me suspect DMAC0 uses both IF0 and IF1 for its DMAs, but that it prefers IF0.
Cheers, Peter
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