Messages in this thread | | | Date | Sat, 26 May 2018 21:45:31 +0800 | From | kbuild test robot <> | Subject | Re: [PATCH v7 5/5] clk: renesas: Renesas R9A06G032 clock driver |
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Hi Michel,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on renesas-drivers/clk-renesas] [also build test WARNING on v4.17-rc6] [cannot apply to robh/for-next] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Michel-Pollet/dt-bindings-Add-the-r9a06g032-sysctrl-h-file/20180526-154235 base: https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git clk-renesas reproduce: # apt-get install sparse make ARCH=x86_64 allmodconfig make C=1 CF=-D__CHECK_ENDIAN__
sparse warnings: (new ones prefixed by >>)
>> drivers/clk/renesas/r9a06g032-clocks.c:430:22: sparse: cast removes address space of expression >> drivers/clk/renesas/r9a06g032-clocks.c:431:30: sparse: incorrect type in argument 1 (different address spaces) @@ expected unsigned int [noderef] [usertype] <asn:2>*reg @@ got eref] [usertype] <asn:2>*reg @@ drivers/clk/renesas/r9a06g032-clocks.c:431:30: expected unsigned int [noderef] [usertype] <asn:2>*reg drivers/clk/renesas/r9a06g032-clocks.c:431:30: got unsigned int [usertype] *reg drivers/clk/renesas/r9a06g032-clocks.c:516:22: sparse: cast removes address space of expression drivers/clk/renesas/r9a06g032-clocks.c:528:38: sparse: incorrect type in argument 2 (different address spaces) @@ expected unsigned int [noderef] [usertype] <asn:2>*reg @@ got eref] [usertype] <asn:2>*reg @@ drivers/clk/renesas/r9a06g032-clocks.c:528:38: expected unsigned int [noderef] [usertype] <asn:2>*reg drivers/clk/renesas/r9a06g032-clocks.c:528:38: got unsigned int [usertype] *reg
vim +430 drivers/clk/renesas/r9a06g032-clocks.c
421 422 #define to_r9a06g032_divider(_hw) \ 423 container_of(_hw, struct r9a06g032_clk_div, hw) 424 425 static unsigned long r9a06g032_divider_recalc_rate( 426 struct clk_hw *hw, 427 unsigned long parent_rate) 428 { 429 struct r9a06g032_clk_div *clk = to_r9a06g032_divider(hw); > 430 u32 *reg = ((u32 *)clk->clocks->reg) + clk->reg; > 431 long div = clk_readl(reg); 432 433 if (div < clk->min) 434 div = clk->min; 435 else if (div > clk->max) 436 div = clk->max; 437 return DIV_ROUND_UP(parent_rate, div); 438 } 439
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