Messages in this thread | | | From | Stephen Boyd <> | Subject | Re: [PATCH v1] clk: mediatek: correct the clocks for MT2701 HDMI PHY module | Date | Tue, 15 May 2018 15:19:02 -0700 |
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Quoting Ryder Lee (2018-04-17 05:30:27) > The hdmitx_dig_cts clock signal is not a child of clk26m, > and the actual output of the PLL block is derived from > the tvdpll via a configurable PLL post-divider. > > It is used as the PLL reference input to the HDMI PHY module. > > Fixes: e9862118272a ("clk: mediatek: Add MT2701 clock support") > Signed-off-by: Chunhui Dai <chunhui.dai@mediatek.com> > Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> > ---
Applied to clk-next
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