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    Subject[PATCH V5 4/6] ARM: dts: imx6sx-sabreauto: add fec support
    Date
    Add FEC support on i.MX6SX Sabre Auto board.

    Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
    ---
    changes since V4:
    add fec gpio regulator and set its default value to LOW for 1.5V IO purpose.
    arch/arm/boot/dts/imx6sx-sabreauto.dts | 80 ++++++++++++++++++++++++++++++++++
    1 file changed, 80 insertions(+)

    diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts b/arch/arm/boot/dts/imx6sx-sabreauto.dts
    index 812f40b..088a66c 100644
    --- a/arch/arm/boot/dts/imx6sx-sabreauto.dts
    +++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
    @@ -23,6 +23,17 @@
    #address-cells = <1>;
    #size-cells = <0>;

    + reg_fec: fec_io_supply {
    + compatible = "regulator-gpio";
    + regulator-name = "1.8V_1.5V_FEC";
    + regulator-min-microvolt = <1500000>;
    + regulator-max-microvolt = <1800000>;
    + states = <1500000 0x0 1800000 0x1>;
    + enable-gpio = <&max7322 0 GPIO_ACTIVE_HIGH>;
    + vin-supply = <&sw2_reg>;
    + enable-active-high;
    + };
    +
    vcc_sd3: regulator@0 {
    compatible = "regulator-fixed";
    reg = <0>;
    @@ -41,6 +52,39 @@
    clock-frequency = <24576000>;
    };

    +&fec1 {
    + pinctrl-names = "default";
    + pinctrl-0 = <&pinctrl_enet1_1>;
    + phy-mode = "rgmii";
    + phy-handle = <&ethphy1>;
    + fsl,magic-packet;
    + status = "okay";
    +
    + mdio {
    + #address-cells = <1>;
    + #size-cells = <0>;
    +
    + ethphy0: ethernet-phy@0 {
    + compatible = "ethernet-phy-ieee802.3-c22";
    + reg = <0>;
    + };
    +
    + ethphy1: ethernet-phy@1 {
    + compatible = "ethernet-phy-ieee802.3-c22";
    + reg = <1>;
    + };
    + };
    +};
    +
    +&fec2 {
    + pinctrl-names = "default";
    + pinctrl-0 = <&pinctrl_enet2_1>;
    + phy-mode = "rgmii";
    + phy-handle = <&ethphy0>;
    + fsl,magic-packet;
    + status = "okay";
    +};
    +
    &uart1 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_uart1>;
    @@ -75,6 +119,42 @@
    &iomuxc {
    imx6x-sabreauto {

    + pinctrl_enet1_1: enet1grp-1 {
    + fsl,pins = <
    + MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
    + MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
    + MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9
    + MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
    + MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
    + MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
    + MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
    + MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
    + MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
    + MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
    + MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
    + MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
    + MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
    + MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
    + >;
    + };
    +
    + pinctrl_enet2_1: enet2grp-1 {
    + fsl,pins = <
    + MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
    + MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
    + MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
    + MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
    + MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
    + MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
    + MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
    + MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
    + MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
    + MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
    + MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
    + MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
    + >;
    + };
    +
    pinctrl_i2c2_1: i2c2grp-1 {
    fsl,pins = <
    MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
    --
    2.7.4
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