Messages in this thread Patch in this message | | | From | David Wang <> | Subject | [PATCH v2] x86/centaur: report correct CPU/cache topology | Date | Wed, 25 Apr 2018 16:48:30 +0800 |
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Centaur CPUs enumerate the cache topology in the same way as Intel CPUs, but the functionality is unused so far. The Centaur init code also misses to initialize x86_info::max_cores, so the CPU topology can't be described correctly.
Initialize x86_cpuinfo:max_core and invoke init_intel_cacheinfo() to make CPU and cache topology information avaliable and correct.
Signed-off-by: David Wang <davidwang@zhaoxin.com>
Changes from v1 to v2: *1 replace centaur_num_cpu_cores with early_init_centaur_mc according to suggestions from tglx; *2 call cpu_detect_cache_sizes when init_intel_cacheinfo returns 0. For some very old Centaur CPUs can't support the mechanisms defined in init_ intel_cacheinfo.
--- arch/x86/kernel/cpu/centaur.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+)
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c index 80d5110..367540b 100644 --- a/arch/x86/kernel/cpu/centaur.c +++ b/arch/x86/kernel/cpu/centaur.c @@ -96,8 +96,25 @@ enum { EAMD3D = 1<<20, }; +static void early_init_centaur_mc(struct cpuinfo_x86 *c) +{ +#ifdef CONFIG_SMP + unsigned int eax, ebx, ecx, edx; + + if (c->cpuid_level < 4) + return; + + cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); + if (eax & 0x1f) + c->x86_max_cores = (eax >> 26) + 1; + else + return; +#endif +} + static void early_init_centaur(struct cpuinfo_x86 *c) { + early_init_centaur_mc(c); switch (c->x86) { #ifdef CONFIG_X86_32 case 5: @@ -146,6 +163,7 @@ static void centaur_detect_vmx_virtcap(struct cpuinfo_x86 *c) static void init_centaur(struct cpuinfo_x86 *c) { + unsigned int l2 = 0; #ifdef CONFIG_X86_32 char *name; u32 fcr_set = 0; @@ -161,6 +179,17 @@ static void init_centaur(struct cpuinfo_x86 *c) #endif early_init_centaur(c); + l2 = init_intel_cacheinfo(c); + + /* Detect legacy cache sizes if init_intel_cacheinfo did not */ + if (l2 == 0) { + cpu_detect_cache_sizes(c); + } + +#ifdef CONFIG_X86_32 + detect_ht(c); +#endif + if (c->cpuid_level > 9) { unsigned int eax = cpuid_eax(10); -- 1.9.1
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