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SubjectRe: [PATCH v3 1/2] perf: riscv: preliminary RISC-V support
On Tue, Apr 17, 2018 at 1:38 AM, Alan Kao <alankao@andestech.com> wrote:

> +static inline void write_counter(int idx, u64 value)
> +{
> + /* currently not supported */
> +}

CSR writes can be emulated: https://github.com/riscv/riscv-pk/pull/98

Or at least write_counter() should have BUG() or WARN_ONCE() or
something like that.

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