Messages in this thread Patch in this message | | | From | Sergey Suloev <> | Subject | [PATCH v2 5/6] spi: sun6i: introduce register set/unset helpers | Date | Fri, 30 Mar 2018 15:50:46 +0300 |
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Two helper functions were added in order to update registers easily.
Signed-off-by: Sergey Suloev <ssuloev@orpaltech.com>
--- drivers/spi/spi-sun6i.c | 39 +++++++++++++++++---------------------- 1 file changed, 17 insertions(+), 22 deletions(-)
diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c index 210cef9..18f9344 100644 --- a/drivers/spi/spi-sun6i.c +++ b/drivers/spi/spi-sun6i.c @@ -115,29 +115,29 @@ static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value) writel(value, sspi->base_addr + reg); } -static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi) +static inline void sun6i_spi_set(struct sun6i_spi *sspi, u32 addr, u32 val) { - u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG); - - reg >>= SUN6I_FIFO_STA_TF_CNT_BITS; + u32 reg = sun6i_spi_read(sspi, addr); - return reg & SUN6I_FIFO_STA_TF_CNT_MASK; + reg |= val; + sun6i_spi_write(sspi, addr, reg); } -static inline void sun6i_spi_enable_interrupt(struct sun6i_spi *sspi, u32 mask) +static inline void sun6i_spi_unset(struct sun6i_spi *sspi, u32 addr, u32 val) { - u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG); + u32 reg = sun6i_spi_read(sspi, addr); - reg |= mask; - sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg); + reg &= ~val; + sun6i_spi_write(sspi, addr, reg); } -static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask) +static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi) { - u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG); + u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG); - reg &= ~mask; - sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg); + reg >>= SUN6I_FIFO_STA_TF_CNT_BITS; + + return reg & SUN6I_FIFO_STA_TF_CNT_MASK; } static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len) @@ -299,18 +299,14 @@ static int sun6i_spi_transfer_one(struct spi_master *master, sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST); - - reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); /* * If it's a TX only transfer, we don't want to fill the RX * FIFO with bogus data */ if (sspi->rx_buf) - reg &= ~SUN6I_TFR_CTL_DHB; + sun6i_spi_unset(sspi, SUN6I_TFR_CTL_REG, SUN6I_TFR_CTL_DHB); else - reg |= SUN6I_TFR_CTL_DHB; - - sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); + sun6i_spi_set(sspi, SUN6I_TFR_CTL_REG, SUN6I_TFR_CTL_DHB); /* Ensure that we have a parent clock fast enough */ @@ -361,11 +357,10 @@ static int sun6i_spi_transfer_one(struct spi_master *master, sun6i_spi_fill_fifo(sspi, sspi->fifo_depth); /* Enable transfer complete interrupt */ - sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TC); + sun6i_spi_set(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC); /* Start the transfer */ - reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); - sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH); + sun6i_spi_set(sspi, SUN6I_TFR_CTL_REG, SUN6I_TFR_CTL_XCH); /* Wait for completion */ ret = sun6i_spi_wait_for_transfer(spi, tfr); -- 2.16.2
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