Messages in this thread | | | Subject | Re: [PATCH v2 1/4] clk: qcom: Clear hardware clock control bit of RCG | From | "Nischal, Amit" <> | Date | Mon, 26 Mar 2018 10:49:47 +0530 |
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On 3/20/2018 4:25 AM, Stephen Boyd wrote: > Quoting Amit Nischal (2018-03-07 23:18:12) >> For upcoming targets like sdm845, POR value of the hardware clock control >> bit is set for most of root clocks which needs to be cleared for software >> to be able to control. For older targets like MSM8996, this bit is reserved >> bit and having POR value as 0 so this patch will work for the older targets >> too. So update the configuration mask to take care of the same to clear >> hardware clock control bit. >> >> Signed-off-by: Amit Nischal <anischal@codeaurora.org> >> --- >> drivers/clk/qcom/clk-rcg2.c | 5 +++-- >> 1 file changed, 3 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c >> index bbeaf9c..e63db10 100644 >> --- a/drivers/clk/qcom/clk-rcg2.c >> +++ b/drivers/clk/qcom/clk-rcg2.c >> @@ -1,5 +1,5 @@ >> /* >> - * Copyright (c) 2013, The Linux Foundation. All rights reserved. >> + * Copyright (c) 2013, 2018, The Linux Foundation. All rights reserved. > It would be nice if lawyers over there could avoid forcing copyright > date updates when less than half the file changes.
Thanks for the review. I will address the above in the next patch series.
> >> * >> * This software is licensed under the terms of the GNU General Public >> * License version 2, as published by the Free Software Foundation, and >> @@ -42,6 +42,7 @@ >> #define CFG_MODE_SHIFT 12 >> #define CFG_MODE_MASK (0x3 << CFG_MODE_SHIFT) >> #define CFG_MODE_DUAL_EDGE (0x2 << CFG_MODE_SHIFT) >> +#define CFG_HW_CLK_CTRL_MASK BIT(20) >> >> #define M_REG 0x8 >> #define N_REG 0xc >> @@ -276,7 +277,7 @@ static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) >> } >> >> mask = BIT(rcg->hid_width) - 1; >> - mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK; >> + mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK; >> cfg = f->pre_div << CFG_SRC_DIV_SHIFT; >> cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; >> if (rcg->mnd_width && f->n && (f->m != f->n)) > Is there going to be a future patch to update the RCGs to indicate they > support hardware control or not?
As of now, there will not be any patch to update the RCGs to support HW control.
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