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    Subject[PATCH 4.14 66/77] dmaengine: ti-dma-crossbar: Fix event mapping for TPCC_EVT_MUX_60_63
    Date
    4.14-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Vignesh R <vigneshr@ti.com>


    [ Upstream commit d087f15786021a9605b20f4c678312510be4cac1 ]

    Register layout of a typical TPCC_EVT_MUX_M_N register is such that the
    lowest numbered event is at the lowest byte address and highest numbered
    event at highest byte address. But TPCC_EVT_MUX_60_63 register layout is
    different, in that the lowest numbered event is at the highest address
    and highest numbered event is at the lowest address. Therefore, modify
    ti_am335x_xbar_write() to handle TPCC_EVT_MUX_60_63 register
    accordingly.

    Signed-off-by: Vignesh R <vigneshr@ti.com>
    Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
    Signed-off-by: Vinod Koul <vinod.koul@intel.com>
    Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    drivers/dma/ti-dma-crossbar.c | 10 +++++++++-
    1 file changed, 9 insertions(+), 1 deletion(-)

    --- a/drivers/dma/ti-dma-crossbar.c
    +++ b/drivers/dma/ti-dma-crossbar.c
    @@ -54,7 +54,15 @@ struct ti_am335x_xbar_map {

    static inline void ti_am335x_xbar_write(void __iomem *iomem, int event, u8 val)
    {
    - writeb_relaxed(val, iomem + event);
    + /*
    + * TPCC_EVT_MUX_60_63 register layout is different than the
    + * rest, in the sense, that event 63 is mapped to lowest byte
    + * and event 60 is mapped to highest, handle it separately.
    + */
    + if (event >= 60 && event <= 63)
    + writeb_relaxed(val, iomem + (63 - event % 4));
    + else
    + writeb_relaxed(val, iomem + event);
    }

    static void ti_am335x_xbar_free(struct device *dev, void *route_data)

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