Messages in this thread | | | Date | Tue, 20 Mar 2018 10:09:31 +0100 | From | Peter Zijlstra <> | Subject | Re: [PATCH] x86/ioapic: don't use unstable TSC to detect timer IRQ |
| |
On Tue, Mar 20, 2018 at 04:58:35PM +0800, Liu, Changcheng wrote: > On 09:49 Tue 20 Mar, Peter Zijlstra wrote: > > On Tue, Mar 20, 2018 at 04:42:55PM +0800, Liu, Changcheng wrote: > > > In rare case, the TSC is every unstable or can't sync with > > > real time hardware clock. > > > > However did you manage that? Please provide _FAR_ more details.
> [Changcheng] TSC is simulated and HPET is hardware implemented. > TSC can't sync with HPET. When running linux, the TSC grows too > fast and HPET can't trigger periodic timer interrupt in time which > is used to update jiffies.
How is that not utterly broken, and how is that even allowed behaviour as per the SDM ?
If the TSC is so utterly broken as to not function according to spec, you should not advertise the TSC, at which point you'll find that it is _very_ hard to run modern linux on x86 without TSC.
| |