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    SubjectRe: [RFC PATCH] KVM: arm/arm64: vgic: change condition for level interrupt resampling
    On Sat, Mar 10, 2018 at 12:20 PM, Marc Zyngier <marc.zyngier@arm.com> wrote:
    > On Fri, 09 Mar 2018 21:36:12 +0000,
    > Christoffer Dall wrote:
    >>
    >> On Thu, Mar 08, 2018 at 05:28:44PM +0000, Marc Zyngier wrote:
    >> > I'd be more confident if we did forbid P+A for such interrupts
    >> > altogether, as they really feel like another kind of HW interrupt.
    >>
    >> How about a slightly bigger hammer: Can we avoid doing P+A for level
    >> interrupts completely? I don't think that really makes much sense, and
    >> I think we simply everything if we just come back out and resample the
    >> line. For an edge, something like a network card, there's a potential
    >> performance win to appending a new pending state, but I doubt that this
    >> is the case for level interrupts.
    >
    > I started implementing the same thing yesterday. Somehow, it feels
    > slightly better to have the same flow for all level interrupts,
    > including the timer, and we only use the MI on EOI as a way to trigger
    > the next state of injection. Still testing, but looking good so far.
    >
    > I'm still puzzled that we have this level-but-not-quite behaviour for
    > VFIO interrupts. At some point, it is going to bite us badly.
    >

    Where is the departure from level-triggered behavior with VFIO? As
    far as I can tell, the GIC flow of the interrupts will be just a level
    interrupt, but we just need to make sure the resamplefd mechanism is
    supported for both types of interrupts. Whether or not that's a
    decent mechanism seems orthogonal to me, but that's a discussion for
    another day I think.

    Thanks,
    -Christoffer

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