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SubjectRe: [PATCH 3/3] PCI: designware-ep: Return an error when requesting a too large BAR size
On Tue, Feb 06, 2018 at 09:38:09PM +0200, Andy Shevchenko wrote:
> On Mon, Feb 5, 2018 at 6:25 PM, Niklas Cassel <niklas.cassel@axis.com> wrote:
> > On Thu, Feb 01, 2018 at 02:00:40PM -0500, Jingoo Han wrote:
> >> On Thursday, February 1, 2018 1:58 PM, Andy Shevchenko wrote:
> >> >
> >> > On Thu, Feb 1, 2018 at 6:11 PM, Niklas Cassel <niklas.cassel@axis.com>
> >> > wrote:
> >> >
> >> > include/linux/sizes.h:
> >> >
> >> > +SZ_4G 0x100000000ULL
> >> >
> >> > > + if (size > 0x100000000ULL) {
> >> >
> >> > #include <linux/sizes.h>
> >> >
> >> > if (size > SZ_4G) {
> >>
> >> I like this one for the readability.
> >> Thank you.
> >>
> >
> > I liked it too, however both variants
> >
> > if (size > 0x100000000ULL) {
> >
> > if (size > SZ_4G) {
> >
> > result in:
> >
> > drivers/pci/dwc/pcie-designware-ep.c:131:11: warning:
> > comparison is always false due to limited range of data type [-Wtype-limits]
> >
> > when compiling with W=1 on a platform with 32-bit size_t.
> >
> >
> > The annoying thing here is that a BAR can be 64-bit,
> > yet the parameter size is defined as a size_t,
> > so the error will only show on 32-bit and not on 64-bit.
>
> Oh, indeed. And it looks moving to u64 or alike is not a solution
> (because if would not describe real hardware in that case).
>
> > What do you think about:
>
> > if (upper_32_bits(size)) {
> > dev_err(pci->dev, "can't handle BAR larger than 4GB\n");
> > return -EINVAL;
> > }
> >
> > That should compile without warnings for both
> > 32-bit size_t and 64-bit size_t.
>
> Can you derive some helper based on the code in __pci_read_base() code?

Hello Andy,

I guess that would be possible, however I think that
simply checking upper_32_bits(size) is simpler.

If someone is ever to fix dw_pcie_ep_set_bar()
so that it works with 64-bit BARs, the function will
probably need to check upper_32_bits(size) anyway.


Regards,
Niklas

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