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    Subject[PATCH 4.14 60/64] KVM/VMX: Emulate MSR_IA32_ARCH_CAPABILITIES
    Date
    4.14-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: KarimAllah Ahmed karahmed@amazon.de

    commit 28c1c9fabf48d6ad596273a11c46e0d0da3e14cd

    Intel processors use MSR_IA32_ARCH_CAPABILITIES MSR to indicate RDCL_NO
    (bit 0) and IBRS_ALL (bit 1). This is a read-only MSR. By default the
    contents will come directly from the hardware, but user-space can still
    override it.

    [dwmw2: The bit in kvm_cpuid_7_0_edx_x86_features can be unconditional]

    Signed-off-by: KarimAllah Ahmed <karahmed@amazon.de>
    Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
    Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
    Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
    Reviewed-by: Darren Kenny <darren.kenny@oracle.com>
    Reviewed-by: Jim Mattson <jmattson@google.com>
    Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
    Cc: Andrea Arcangeli <aarcange@redhat.com>
    Cc: Andi Kleen <ak@linux.intel.com>
    Cc: Jun Nakajima <jun.nakajima@intel.com>
    Cc: kvm@vger.kernel.org
    Cc: Dave Hansen <dave.hansen@intel.com>
    Cc: Linus Torvalds <torvalds@linux-foundation.org>
    Cc: Andy Lutomirski <luto@kernel.org>
    Cc: Asit Mallick <asit.k.mallick@intel.com>
    Cc: Arjan Van De Ven <arjan.van.de.ven@intel.com>
    Cc: Greg KH <gregkh@linuxfoundation.org>
    Cc: Dan Williams <dan.j.williams@intel.com>
    Cc: Tim Chen <tim.c.chen@linux.intel.com>
    Cc: Ashok Raj <ashok.raj@intel.com>
    Link: https://lkml.kernel.org/r/1517522386-18410-4-git-send-email-karahmed@amazon.de
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>


    ---
    arch/x86/kvm/cpuid.c | 2 +-
    arch/x86/kvm/vmx.c | 15 +++++++++++++++
    arch/x86/kvm/x86.c | 1 +
    3 files changed, 17 insertions(+), 1 deletion(-)

    --- a/arch/x86/kvm/cpuid.c
    +++ b/arch/x86/kvm/cpuid.c
    @@ -394,7 +394,7 @@ static inline int __do_cpuid_ent(struct

    /* cpuid 7.0.edx*/
    const u32 kvm_cpuid_7_0_edx_x86_features =
    - F(AVX512_4VNNIW) | F(AVX512_4FMAPS);
    + F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(ARCH_CAPABILITIES);

    /* all calls to cpuid_count() should be made on the same cpu */
    get_cpu();
    --- a/arch/x86/kvm/vmx.c
    +++ b/arch/x86/kvm/vmx.c
    @@ -583,6 +583,8 @@ struct vcpu_vmx {
    u64 msr_guest_kernel_gs_base;
    #endif

    + u64 arch_capabilities;
    +
    u32 vm_entry_controls_shadow;
    u32 vm_exit_controls_shadow;
    u32 secondary_exec_control;
    @@ -3257,6 +3259,12 @@ static int vmx_get_msr(struct kvm_vcpu *
    case MSR_IA32_TSC:
    msr_info->data = guest_read_tsc(vcpu);
    break;
    + case MSR_IA32_ARCH_CAPABILITIES:
    + if (!msr_info->host_initiated &&
    + !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
    + return 1;
    + msr_info->data = to_vmx(vcpu)->arch_capabilities;
    + break;
    case MSR_IA32_SYSENTER_CS:
    msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
    break;
    @@ -3392,6 +3400,11 @@ static int vmx_set_msr(struct kvm_vcpu *
    vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
    MSR_TYPE_W);
    break;
    + case MSR_IA32_ARCH_CAPABILITIES:
    + if (!msr_info->host_initiated)
    + return 1;
    + vmx->arch_capabilities = data;
    + break;
    case MSR_IA32_CR_PAT:
    if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
    if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
    @@ -5652,6 +5665,8 @@ static int vmx_vcpu_setup(struct vcpu_vm
    ++vmx->nmsrs;
    }

    + if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
    + rdmsrl(MSR_IA32_ARCH_CAPABILITIES, vmx->arch_capabilities);

    vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);

    --- a/arch/x86/kvm/x86.c
    +++ b/arch/x86/kvm/x86.c
    @@ -1006,6 +1006,7 @@ static u32 msrs_to_save[] = {
    #endif
    MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
    MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
    + MSR_IA32_ARCH_CAPABILITIES
    };

    static unsigned num_msrs_to_save;

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