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    Subject[PATCH AUTOSEL for 3.18 08/24] tg3: Add workaround to restrict 5762 MRRS to 2048
    Date
    From: Siva Reddy Kallam <siva.kallam@broadcom.com>

    [ Upstream commit 4419bb1cedcda0272e1dc410345c5a1d1da0e367 ]

    One of AMD based server with 5762 hangs with jumbo frame traffic.
    This AMD platform has southbridge limitation which is restricting MRRS
    to 4000. As a work around, driver to restricts the MRRS to 2048 for
    this particular 5762 NX1 card.

    Signed-off-by: Siva Reddy Kallam <siva.kallam@broadcom.com>
    Signed-off-by: Michael Chan <michael.chan@broadcom.com>
    Signed-off-by: David S. Miller <davem@davemloft.net>
    Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
    ---
    drivers/net/ethernet/broadcom/tg3.c | 10 ++++++++++
    drivers/net/ethernet/broadcom/tg3.h | 4 ++++
    2 files changed, 14 insertions(+)

    diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
    index 05a2f3b304c3..e0b446525f53 100644
    --- a/drivers/net/ethernet/broadcom/tg3.c
    +++ b/drivers/net/ethernet/broadcom/tg3.c
    @@ -10028,6 +10028,16 @@ static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)

    tw32(GRC_MODE, tp->grc_mode | val);

    + /* On one of the AMD platform, MRRS is restricted to 4000 because of
    + * south bridge limitation. As a workaround, Driver is setting MRRS
    + * to 2048 instead of default 4096.
    + */
    + if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
    + tp->pdev->subsystem_device == TG3PCI_SUBDEVICE_ID_DELL_5762) {
    + val = tr32(TG3PCI_DEV_STATUS_CTRL) & ~MAX_READ_REQ_MASK;
    + tw32(TG3PCI_DEV_STATUS_CTRL, val | MAX_READ_REQ_SIZE_2048);
    + }
    +
    /* Setup the timer prescalar register. Clock is always 66Mhz. */
    val = tr32(GRC_MISC_CFG);
    val &= ~0xff;
    diff --git a/drivers/net/ethernet/broadcom/tg3.h b/drivers/net/ethernet/broadcom/tg3.h
    index 31c9f8295953..19532961e173 100644
    --- a/drivers/net/ethernet/broadcom/tg3.h
    +++ b/drivers/net/ethernet/broadcom/tg3.h
    @@ -95,6 +95,7 @@
    #define TG3PCI_SUBDEVICE_ID_DELL_JAGUAR 0x0106
    #define TG3PCI_SUBDEVICE_ID_DELL_MERLOT 0x0109
    #define TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT 0x010a
    +#define TG3PCI_SUBDEVICE_ID_DELL_5762 0x07f0
    #define TG3PCI_SUBVENDOR_ID_COMPAQ PCI_VENDOR_ID_COMPAQ
    #define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE 0x007c
    #define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2 0x009a
    @@ -280,6 +281,9 @@
    #define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */
    #define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */
    /* 0xa8 --> 0xb8 unused */
    +#define TG3PCI_DEV_STATUS_CTRL 0x000000b4
    +#define MAX_READ_REQ_SIZE_2048 0x00004000
    +#define MAX_READ_REQ_MASK 0x00007000
    #define TG3PCI_DUAL_MAC_CTRL 0x000000b8
    #define DUAL_MAC_CTRL_CH_MASK 0x00000003
    #define DUAL_MAC_CTRL_ID 0x00000004
    --
    2.11.0
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