Messages in this thread Patch in this message | | | From | Ashok Raj <> | Subject | [PATCH 2/3] x86/microcode/intel: Perform a cache flush before ucode update. | Date | Wed, 21 Feb 2018 08:49:43 -0800 |
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Microcode updates can be safer if the caches are clean. Some of the issues around in certain Broadwell parts can be addressed by doing a full cache flush.
Signed-off-by: Ashok Raj <ashok.raj@intel.com> Cc: X86 ML <x86@kernel.org> Cc: LKML <linux-kernel@vger.kernel.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@kernel.org> Cc: Tony Luck <tony.luck@intel.com> Cc: Andi Kleen <andi.kleen@intel.com> Cc: Boris Petkov <bp@suse.de> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Arjan Van De Ven <arjan.van.de.ven@intel.com> --- arch/x86/kernel/cpu/microcode/intel.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index eff80df..5d32724 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -589,6 +589,7 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) if (!mc) return 0; + wbinvd(); /* write microcode via MSR 0x79 */ native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); @@ -805,6 +806,7 @@ static enum ucode_state apply_microcode_intel(int cpu) return UCODE_OK; } + wbinvd(); /* write microcode via MSR 0x79 */ wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); -- 2.7.4
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