Messages in this thread | | | Date | Wed, 14 Feb 2018 17:52:48 +0200 | From | Mika Westerberg <> | Subject | Re: [PATCH 18/18] thunderbolt: Add support for Intel Titan Ridge |
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On Wed, Feb 14, 2018 at 04:29:54PM +0200, Andy Shevchenko wrote: > On Wed, Feb 14, 2018 at 4:28 PM, Mika Westerberg > <mika.westerberg@linux.intel.com> wrote: > > On Wed, Feb 14, 2018 at 04:23:44PM +0200, Andy Shevchenko wrote: > >> On Tue, Feb 13, 2018 at 7:00 PM, Mika Westerberg > >> <mika.westerberg@linux.intel.com> wrote: > > >> > +static inline u64 get_parent_route(u64 route) > >> > +{ > >> > + int depth = tb_route_length(route); > >> > + return depth ? route & ~((u64)0xff << (depth - 1) * TB_ROUTE_SHIFT) : 0; > >> > >> 0xffULL ? > > Agreed or not?
Agreed :)
> >> > #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI 0x15dc > >> > #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI 0x15dd > >> > #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI 0x15de > >> > >> > +#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI 0x15e8 > >> > +#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_BRIDGE 0x15e7 > >> > +#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI 0x15eb > >> > +#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_BRIDGE 0x15ea > >> > +#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_BRIDGE 0x15ef > >> > >> Can we keep it sorted? > > > > It is sorted by the controller type ;-) > > Yes, this is not what I'm talking about. Inside the group you can > easily keep it sorted.
OK, that works for me.
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