Messages in this thread | | | Date | Tue, 13 Feb 2018 10:43:56 +0100 | From | Ingo Molnar <> | Subject | Re: [tip:x86/boot] x86/boot/compressed/64: Handle 5-level paging boot if kernel is above 4G |
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* Kirill A. Shutemov <kirill@shutemov.name> wrote:
> On Tue, Feb 13, 2018 at 12:41:22AM -0800, Andrei Vagin wrote: > > On Tue, Feb 13, 2018 at 11:08:16AM +0300, Kirill A. Shutemov wrote: > > > On Mon, Feb 12, 2018 at 10:51:56PM -0800, Andrei Vagin wrote: > > > > Hi Kirill, > > > > > > > > Something is wrong in this patch. > > Could you please check if this makes a difference? > > diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S > index 70b30f2bc9e0..99a0e7993252 100644 > --- a/arch/x86/boot/compressed/head_64.S > +++ b/arch/x86/boot/compressed/head_64.S > @@ -332,7 +332,7 @@ ENTRY(startup_64) > > /* Make sure we have GDT with 32-bit code segment */ > leaq gdt(%rip), %rax > - movl %eax, gdt64+2(%rip) > + movq %rax, gdt64+2(%rip) > lgdt gdt64(%rip)
There's another suspicious looking pattern as well:
leaq startup_32(%rip), %rax movl %eax, BP_code32_start(%rsi) ... movl BP_code32_start(%esi), %eax leaq startup_64(%rax), %rax ...
Thanks,
Ingo
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