lkml.org 
[lkml]   [2018]   [Dec]   [5]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH AUTOSEL 4.19 049/123] phy: qcom-qusb2: Use HSTX_TRIM fused value as is
    Date
    From: Manu Gautam <mgautam@codeaurora.org>

    [ Upstream commit 6e34d358b24ffc40764eb3681164c79091765429 ]

    Fix HSTX_TRIM tuning logic which instead of using fused value
    as HSTX_TRIM, incorrectly performs bitwise OR operation with
    existing default value.

    Fixes: ca04d9d3e1b1 ("phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips")
    Signed-off-by: Manu Gautam <mgautam@codeaurora.org>
    Reviewed-by: Douglas Anderson <dianders@chromium.org>
    Reviewed-by: Stephen Boyd <swboyd@chromium.org>
    Acked-by: Vivek Gautam <vivek.gautam@codeaurora.org>
    Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/phy/qualcomm/phy-qcom-qusb2.c | 19 ++++++++++---------
    1 file changed, 10 insertions(+), 9 deletions(-)

    diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
    index e70e425f26f5..9d6c88064158 100644
    --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
    +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
    @@ -402,10 +402,10 @@ static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)

    /*
    * Read efuse register having TUNE2/1 parameter's high nibble.
    - * If efuse register shows value as 0x0, or if we fail to find
    - * a valid efuse register settings, then use default value
    - * as 0xB for high nibble that we have already set while
    - * configuring phy.
    + * If efuse register shows value as 0x0 (indicating value is not
    + * fused), or if we fail to find a valid efuse register setting,
    + * then use default value for high nibble that we have already
    + * set while configuring the phy.
    */
    val = nvmem_cell_read(qphy->cell, NULL);
    if (IS_ERR(val) || !val[0]) {
    @@ -415,12 +415,13 @@ static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)

    /* Fused TUNE1/2 value is the higher nibble only */
    if (cfg->update_tune1_with_efuse)
    - qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
    - val[0] << 0x4);
    + qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
    + val[0] << HSTX_TRIM_SHIFT,
    + HSTX_TRIM_MASK);
    else
    - qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
    - val[0] << 0x4);
    -
    + qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
    + val[0] << HSTX_TRIM_SHIFT,
    + HSTX_TRIM_MASK);
    }

    static int qusb2_phy_set_mode(struct phy *phy, enum phy_mode mode)
    --
    2.17.1
    \
     
     \ /
      Last update: 2018-12-05 10:39    [W:2.297 / U:0.088 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site