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    Subject[PATCH 4.19 081/139] PCI: Fix incorrect value returned from pcie_get_speed_cap()
    Date
    4.19-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Mikulas Patocka <mpatocka@redhat.com>

    commit f1f90e254e46e0a14220e4090041f68256fbe297 upstream.

    The macros PCI_EXP_LNKCAP_SLS_*GB are values, not bit masks. We must mask
    the register and compare it against them.

    This fixes errors like this:

    amdgpu: [powerplay] failed to send message 261 ret is 0

    when a PCIe-v3 card is plugged into a PCIe-v1 slot, because the slot is
    being incorrectly reported as PCIe-v3 capable.

    6cf57be0f78e, which appeared in v4.17, added pcie_get_speed_cap() with the
    incorrect test of PCI_EXP_LNKCAP_SLS as a bitmask. 5d9a63304032, which
    appeared in v4.19, changed amdgpu to use pcie_get_speed_cap(), so the
    amdgpu bug reports below are regressions in v4.19.

    Fixes: 6cf57be0f78e ("PCI: Add pcie_get_speed_cap() to find max supported link speed")
    Fixes: 5d9a63304032 ("drm/amdgpu: use pcie functions for link width and speed")
    Link: https://bugs.freedesktop.org/show_bug.cgi?id=108704
    Link: https://bugs.freedesktop.org/show_bug.cgi?id=108778
    Signed-off-by: Mikulas Patocka <mpatocka@redhat.com>
    [bhelgaas: update comment, remove use of PCI_EXP_LNKCAP_SLS_8_0GB and
    PCI_EXP_LNKCAP_SLS_16_0GB since those should be covered by PCI_EXP_LNKCAP2,
    remove test of PCI_EXP_LNKCAP for zero, since that register is required]
    Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
    Acked-by: Alex Deucher <alexander.deucher@amd.com>
    Cc: stable@vger.kernel.org # v4.17+
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    drivers/pci/pci.c | 24 +++++++++++-------------
    1 file changed, 11 insertions(+), 13 deletions(-)

    --- a/drivers/pci/pci.c
    +++ b/drivers/pci/pci.c
    @@ -5473,9 +5473,13 @@ enum pci_bus_speed pcie_get_speed_cap(st
    u32 lnkcap2, lnkcap;

    /*
    - * PCIe r4.0 sec 7.5.3.18 recommends using the Supported Link
    - * Speeds Vector in Link Capabilities 2 when supported, falling
    - * back to Max Link Speed in Link Capabilities otherwise.
    + * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18. The
    + * implementation note there recommends using the Supported Link
    + * Speeds Vector in Link Capabilities 2 when supported.
    + *
    + * Without Link Capabilities 2, i.e., prior to PCIe r3.0, software
    + * should use the Supported Link Speeds field in Link Capabilities,
    + * where only 2.5 GT/s and 5.0 GT/s speeds were defined.
    */
    pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
    if (lnkcap2) { /* PCIe r3.0-compliant */
    @@ -5491,16 +5495,10 @@ enum pci_bus_speed pcie_get_speed_cap(st
    }

    pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
    - if (lnkcap) {
    - if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB)
    - return PCIE_SPEED_16_0GT;
    - else if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB)
    - return PCIE_SPEED_8_0GT;
    - else if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB)
    - return PCIE_SPEED_5_0GT;
    - else if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB)
    - return PCIE_SPEED_2_5GT;
    - }
    + if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB)
    + return PCIE_SPEED_5_0GT;
    + else if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB)
    + return PCIE_SPEED_2_5GT;

    return PCI_SPEED_UNKNOWN;
    }

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