lkml.org 
[lkml]   [2018]   [Dec]   [28]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
SubjectRe: [Qemu-devel][PATCH 2/4] Add CET SHSTK and IBT CPUID feature-word definitions.
From
Date
On 26/12/18 09:25, Yang Weijiang wrote:
> @@ -1233,6 +1252,14 @@ static const ExtSaveArea x86_ext_save_areas[] = {
> { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
> .offset = offsetof(X86XSaveArea, pkru_state),
> .size = sizeof(XSavePKRU) },
> + [XSTATE_CET_U_BIT] = {
> + .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_CET_SHSTK,
> + .offset = offsetof(X86XSaveArea, cet_u),

These offsets are incorrect, since supervisor states are only stored in
the compacted format. In fact, in patch 4, supervisor states should
return 0 in CPUID(EAX=0Dh,ECX=n).EBX.

You can use offset == 0 to distinguish supervisor and user states, so
that supervisor states are skipped in xsave_area_size and x86_cpu_reset.

Thanks,

Paolo

> + .size = sizeof(XSaveCETU) },
> + [XSTATE_CET_S_BIT] = {
> + .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_CET_SHSTK,
> + .offset = offsetof(X86XSaveArea, cet_s),
> + .size = sizeof(XSaveCETS) },
> };
>
> static uint32_t xsave_area_size(uint64_t mask)

\
 
 \ /
  Last update: 2018-12-28 15:27    [W:0.208 / U:0.496 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site