Messages in this thread | | | Subject | Re: [PATCH 01/13] clk: qcom: gcc: limit GPLL0_AO_OUT operating frequency | From | Taniya Das <> | Date | Fri, 21 Dec 2018 16:49:30 +0530 |
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On 12/17/2018 3:16 PM, Jorge Ramirez-Ortiz wrote: > Limit the GPLL0_AO_OUT_MAIN operating frequency as per its hardware > specifications. > > Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org> > Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> > Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> > --- > drivers/clk/qcom/gcc-qcs404.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c > index 64da032..833436a 100644 > --- a/drivers/clk/qcom/gcc-qcs404.c > +++ b/drivers/clk/qcom/gcc-qcs404.c > @@ -304,10 +304,16 @@ static struct clk_alpha_pll gpll0_out_main = { > }, > }; > > +static const struct pll_vco gpll0_ao_out_vco[] = { > + { 800000000, 800000000, 0 }, > +}; > + > static struct clk_alpha_pll gpll0_ao_out_main = { > .offset = 0x21000, > .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], > .flags = SUPPORTS_FSM_MODE, > + .vco_table = gpll0_ao_out_vco, > + .num_vco = ARRAY_SIZE(gpll0_ao_out_vco),
Could you please help as to why this is required? This is a fixed PLL and we do not require a VCO table for it.
> .clkr = { > .enable_reg = 0x45000, > .enable_mask = BIT(0), >
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