Messages in this thread | | | From | "Liu, Yi L" <> | Subject | RE: [PATCH v4 10/12] iommu/vt-d: Add first level page table interface | Date | Wed, 7 Nov 2018 07:34:47 +0000 |
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Hi Baolu,
> From: Lu Baolu [mailto:baolu.lu@linux.intel.com] > Sent: Monday, November 5, 2018 1:32 PM > Subject: [PATCH v4 10/12] iommu/vt-d: Add first level page table interface > > This adds an interface to setup the PASID entries for first
This patch adds interface to setup the PASID entries for first. :)
> level page table translation. > > Cc: Ashok Raj <ashok.raj@intel.com> > Cc: Jacob Pan <jacob.jun.pan@linux.intel.com> > Cc: Kevin Tian <kevin.tian@intel.com> > Cc: Liu Yi L <yi.l.liu@intel.com> > Signed-off-by: Sanjay Kumar <sanjay.k.kumar@intel.com> > Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> > Reviewed-by: Ashok Raj <ashok.raj@intel.com> > --- > drivers/iommu/intel-pasid.c | 81 +++++++++++++++++++++++++++++++++++++ > drivers/iommu/intel-pasid.h | 11 +++++ > include/linux/intel-iommu.h | 1 + > 3 files changed, 93 insertions(+) > > diff --git a/drivers/iommu/intel-pasid.c b/drivers/iommu/intel-pasid.c > index 69530317c323..d8ca1e6a8e5e 100644 > --- a/drivers/iommu/intel-pasid.c > +++ b/drivers/iommu/intel-pasid.c > @@ -10,6 +10,7 @@ > #define pr_fmt(fmt) "DMAR: " fmt > > #include <linux/bitops.h> > +#include <linux/cpufeature.h> > #include <linux/dmar.h> > #include <linux/intel-iommu.h> > #include <linux/iommu.h> > @@ -388,6 +389,26 @@ static inline void pasid_set_page_snoop(struct pasid_entry > *pe, bool value) > pasid_set_bits(&pe->val[1], 1 << 23, value); > } > > +/* > + * Setup the First Level Page table Pointer field (Bit 140~191) > + * of a scalable mode PASID entry. > + */ > +static inline void > +pasid_set_flptr(struct pasid_entry *pe, u64 value) > +{ > + pasid_set_bits(&pe->val[2], VTD_PAGE_MASK, value); > +} > + > +/* > + * Setup the First Level Paging Mode field (Bit 130~131) of a > + * scalable mode PASID entry. > + */ > +static inline void > +pasid_set_flpm(struct pasid_entry *pe, u64 value) > +{ > + pasid_set_bits(&pe->val[2], GENMASK_ULL(3, 2), value << 2); > +} > + > static void > pasid_cache_invalidation_with_pasid(struct intel_iommu *iommu, > u16 did, int pasid) > @@ -458,6 +479,66 @@ void intel_pasid_tear_down_entry(struct intel_iommu > *iommu, > devtlb_invalidation_with_pasid(iommu, dev, pasid); > } > > +/* > + * Set up the scalable mode pasid table entry for first only > + * translation type. > + */ > +int intel_pasid_setup_first_level(struct intel_iommu *iommu, > + struct device *dev, pgd_t *pgd, > + int pasid, int flags) > +{ > + u16 did = FLPT_DEFAULT_DID; > + struct pasid_entry *pte;
aha, same comment with previous patch. may be better us pt_entry or pasid_entry.
Regards, Yi Liu
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