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    Subject[PATCH 4.4 121/160] MIPS: Loongson-3: Fix BRIDGE irq delivery problem
    Date
    4.4-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    [ Upstream commit 360fe725f8849aaddc53475fef5d4a0c439b05ae ]

    After commit e509bd7da149dc349160 ("genirq: Allow migration of chained
    interrupts by installing default action") Loongson-3 fails at here:

    setup_irq(LOONGSON_HT1_IRQ, &cascade_irqaction);

    This is because both chained_action and cascade_irqaction don't have
    IRQF_SHARED flag. This will cause Loongson-3 resume fails because HPET
    timer interrupt can't be delivered during S3. So we set the irqchip of
    the chained irq to loongson_irq_chip which doesn't disable the chained
    irq in CP0.Status.

    Cc: stable@vger.kernel.org
    Signed-off-by: Huacai Chen <chenhc@lemote.com>
    Signed-off-by: Paul Burton <paul.burton@mips.com>
    Patchwork: https://patchwork.linux-mips.org/patch/20434/
    Cc: Ralf Baechle <ralf@linux-mips.org>
    Cc: James Hogan <jhogan@kernel.org>
    Cc: linux-mips@linux-mips.org
    Cc: Fuxin Zhang <zhangfx@lemote.com>
    Cc: Zhangjin Wu <wuzhangjin@gmail.com>
    Cc: Huacai Chen <chenhuacai@gmail.com>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    arch/mips/include/asm/mach-loongson64/irq.h | 2 +-
    arch/mips/loongson64/loongson-3/irq.c | 13 +++----------
    2 files changed, 4 insertions(+), 11 deletions(-)

    diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h
    index d18c45c7c394..19ff9ce46c02 100644
    --- a/arch/mips/include/asm/mach-loongson64/irq.h
    +++ b/arch/mips/include/asm/mach-loongson64/irq.h
    @@ -9,7 +9,7 @@
    #define MIPS_CPU_IRQ_BASE 56

    #define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 2) /* UART */
    -#define LOONGSON_HT1_IRQ (MIPS_CPU_IRQ_BASE + 3) /* HT1 */
    +#define LOONGSON_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 3) /* CASCADE */
    #define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* CPU Timer */

    #define LOONGSON_HT1_CFG_BASE loongson_sysconf.ht_control_base
    diff --git a/arch/mips/loongson64/loongson-3/irq.c b/arch/mips/loongson64/loongson-3/irq.c
    index 53424f2a53f3..241cb88f9c03 100644
    --- a/arch/mips/loongson64/loongson-3/irq.c
    +++ b/arch/mips/loongson64/loongson-3/irq.c
    @@ -42,12 +42,6 @@ void mach_irq_dispatch(unsigned int pending)
    }
    }

    -static struct irqaction cascade_irqaction = {
    - .handler = no_action,
    - .flags = IRQF_NO_SUSPEND,
    - .name = "cascade",
    -};
    -
    static inline void mask_loongson_irq(struct irq_data *d) { }
    static inline void unmask_loongson_irq(struct irq_data *d) { }

    @@ -88,11 +82,10 @@ void __init mach_init_irq(void)
    init_i8259_irqs();
    irq_set_chip_and_handler(LOONGSON_UART_IRQ,
    &loongson_irq_chip, handle_percpu_irq);
    + irq_set_chip_and_handler(LOONGSON_BRIDGE_IRQ,
    + &loongson_irq_chip, handle_percpu_irq);

    - /* setup HT1 irq */
    - setup_irq(LOONGSON_HT1_IRQ, &cascade_irqaction);
    -
    - set_c0_status(STATUSF_IP2 | STATUSF_IP6);
    + set_c0_status(STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP6);
    }

    #ifdef CONFIG_HOTPLUG_CPU
    --
    2.17.1


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